alonamid

In an ideal world, I would like everything in firechip/rebar to be simulator-agnostic. i.e. Have all the widgets and SimConfigs be in firesim, while firechip/rebar has only SoC components that...

We had the a previous discussion about making this a "monorepo" vs a "lean project template", and it seems like the majority preferred a "monorepo" where everything is integrated and...

AFAIK, a DDR controller is a non-trivial endeavor, but we will be happy to accept a PR for a DDR controller which connects to the Tilelink memory bus.

How long is "long"? Did you have any issues with your internet connections? what is your environment (OS, etc.)? are you on a network file system?

Is this issue persisting? Are you able to reproduce it on another machine? Is a network file system involved anywhere in the process?

I believe this was answered in the following thread: https://groups.google.com/u/1/g/chipyard/c/fHvnRREsV5A

There is not enough information about the error. These are just the final lines of a parallel make run. There should be additional information further up the log. Did you...

Why not connect to the system bus or the periphery bus?

Either way, it seems that there is a higher likelihood that you block is not fully complying to the TileLink protocol assumption when connecting to the bus

What do you mean by "exits immediately" in FireSim? what is the last output you see? Could you also clarify your comment about CVA6 Dhrystone depending on the L2 cache?