Alin-Tudor Sferle

ad7616_sdz_zc706_pi: - modify `adc_db_io` _ad_iobuf_ instantiation similarly to the definition in the ad7616_sdz_zed_pi ad7616_sdc_zed_pi: - Update the conversion start signal to the new name, `adc_cnvst`, in the parallel system_top and...

V2: - Removed the `rx_cnvst_n` signal from axi_ad7606b IP, this being generated using _**axi_pwm_gen**_ module;

V3: - axi_ad7606b IP: Updated up_adc_common and channel instances with _**raw data reading**_ and _**register data reading/writing**_ features; - ad7606b_fmc project: Defined missing pins;

V4: - Rebased to the master branch;

V5: - Updated to latest `up_adc_channel` _**read raw data functionality**_ version;

V6: - Rebased to the `master` branch;

V7: - Updated makefiles;

V8: - Updated project's GPIO pins; - Used generated 100MHz clock from `cpu_clk` as an `external_clk`. Generated for `axi_dmac` and `up_cpack2` modules' clocks ,instead of axi_ad7606b's `adc_clk`;

V9: - renamed `ext_clk` bus in `axi_ad7606b_ip.tcl` definition fiel to `external_clk`; Notes: - Software must control the `adc_reset` pin of AD7606B; - Recommended mode of operation using `adc_os` pins: software...

V10: - [axi_ad7606b: Update up_adc_common and up_adc_channel instances](https://github.com/analogdevicesinc/hdl/pull/1003/commits/1d593b8eca1bfda36f5feb51352a70c798ebf53f);