How can I turn ethernet udp stack to "not" loopback circuit?

[alien2327]

Hello.

First of all, thank you for your awesome verilog codes. I'm not an expert, just a little graduate school student, and I'm trying to make some ADC circuit with VC707 FPGA.

So here are my questions,

1. You shared your ethernet codes with some examples, but I realized that those codes are just looping back recieved packet. If you don't mind, could you tell me how can I swith to "not" loopback circuit? For example, now I'm making some ADC circuit, and I'm going to recive digital signal through FMC cable, and I want to send those data to PC with ethernet. Will it possible make these sort of function with your code?

2. And this is very simple question (because I'm just super newbie..), which line in the code (for example, KC705 sgmii) make these examples loopback circuit?

Again, thank you for your hard and fency works.

[alexforencich]

Basically you'll need to remove and replace the logic at the top-level that handles the UDP packets. There is code that does a simple check on the dest port of the incoming packets, as well as a FIFO for the payload data. This code sits between the UDP packet output and input ports on the main UDP stack module. Remove/modify/etc this code to suit your application.