alexforencich
How to implement 1G on the zcu102 SFP connector?
Hi, thanks for developing this wonderful repo.
I am trying to use the SFP connector interface on the ZCU102 board. But my network devices can only provide up to a 1000Mbps rate for testing. I notice the projects of other boards have several options in different speeds 1G/10G/25G. But for ZCU102, there is only one 10G speed, which seems not to adapt to my 1G network well. I have been trying to migrate the 1G project for VCU108 to ZCU102 for days by changing the configuration of the 1G/2.5G PCS/PMD or SMII IP to 1000BASE standard and modifying the pin assignment. But came across some constraints problems. Such as this one:
[Constraints 18-602] set_output_delay: list contains '1' objects of types '(port)' other than the types '(output port,internal pin)' supported by the constraint. These objects will not be used for this constraint. Please review the object list and ensure unsupported object types are removed. ["/home/yzhengbv/00-data/git/verilog-ethernet/example/ZCU102/fpga_sfp_1g/fpga.xdc":114] [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_ports sfp0_tx_disable_b]'. ["/home/yzhengbv/00-data/git/verilog-ethernet/example/ZCU102/fpga_sfp_1g/fpga.xdc":134] [Common 17-55] 'set_property' expects at least one object. ["/home/yzhengbv/00-data/git/verilog-ethernet/example/ZCU102/fpga_sfp_1g/fpga.xdc":129] [Common 17-55] 'set_property' expects at least one object. ["/home/yzhengbv/00-data/git/verilog-ethernet/example/ZCU102/fpga_sfp_1g/eth.xdc":3] [Vivado 12-4739] set_output_delay:No valid object(s) found for '-objects [get_ports sfp0_tx_disable_b]'. ["/home/yzhengbv/00-data/git/verilog-ethernet/example/ZCU102/fpga_sfp_1g/fpga.xdc":135] [Constraints 18-602] set_input_delay: list contains '1' objects of types '(port)' other than the types '(input port,internal pin)' supported by the constraint. These objects will not be used for this constraint. Please review the object list and ensure unsupported object types are removed. ["/home/yzhengbv/00-data/git/verilog-ethernet/example/ZCU102/fpga_sfp_1g/fpga.xdc":116]
And below are some mentioned lines in my constant files: fpga.xdc:
113 set_false_path -to [get_ports {uart_txd uart_cts}] 114 set_output_delay 0.000 [get_ports {uart_txd uart_cts}] 115 set_false_path -from [get_ports {uart_rxd uart_rts}] 116 set_input_delay 0.000 [get_ports {uart_rxd uart_rts}] 117 118 # SFP+ Interface 119 set_property -dict {LOC D2} [get_ports sfp0_rx_p] 120 set_property -dict {LOC D1} [get_ports sfp0_rx_n] 121 set_property -dict {LOC E4} [get_ports sfp0_tx_p] 122 set_property -dict {LOC E3} [get_ports sfp0_tx_n] 123 set_property -dict {LOC C8} [get_ports sfp_mgt_refclk_0_p] 124 set_property -dict {LOC C7} [get_ports sfp_mgt_refclk_0_n] 125 #set_property -dict {LOC B10 } [get_ports sfp_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U20 CKOUT2 SI 5328 126 #set_property -dict {LOC B9 } [get_ports sfp_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U20 CKOUT2 SI 5328 127 #set_property -dict {LOC R10 IOSTANDARD LVDS} [get_ports sfp_recclk_p] ;# to U20 CKIN1 SI5328 128 #set_property -dict {LOC R9 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to U20 CKIN1 SI5328 129 set_property -dict {LOC A12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports sfp0_tx_disable_b] 130 131 # 156.25 MHz MGT reference clock 132 create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p] 133 134 set_false_path -to [get_ports {sfp0_tx_disable_b}] 135 set_output_delay 0.000 [get_ports {sfp0_tx_disable_b}]
eth.xdc
3 set_property LOC BITSLICE_RX_TX_X1Y35 [get_cells -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/idelay_cal}]
Really appreciate it if you could help with this or provide any other 1G solutions on ZCU102.
Major difference between VCU108/VCU118 and ZCU102 is that the VCU108/VCU118 use IOSERDES, while the ZCU102 uses full GTH transceivers. So you'll have to remove all of the IOSERDES/bitslice specific constraints. I'm also not sure what the story is with clocking for 1000BASE-X, but I think the PLLs in the GTH transceivers should be flexible enough to work with the default 156.25 MHz ref clk.
Also, you can comment out all of the input/output delay constraints, those only serve to remove some warnings on the timing report.
