verilog-axi
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Published
20 hours ago •
alexforencich
alexforencich
Timing issues with `axi_dma_wr`
Basically the same issue as #13, but reposting again due to possible visibility issue...
The path in question as dumped in the timing report is attached at the end. It seems a bit excessive to have 15/16 logic levels and it is a struggle to get it working at around 250 MHz (floorplanning showed limited improvement and is not very stable). Any thoughts @alexforencich?
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) : -0.187ns (required time - arrival time)
Source: design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/offset_reg_reg[2]_replica/C
(rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_0_0 {[email protected] [email protected] period=4.000ns})
Destination: design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/status_fifo_len_reg_0_31_14_15/RAMA_D1/I
(rising edge-triggered cell RAMD32 clocked by clk_out1_design_1_clk_wiz_0_0 {[email protected] [email protected] period=4.000ns})
Path Group: clk_out1_design_1_clk_wiz_0_0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 4.000ns (clk_out1_design_1_clk_wiz_0_0 [email protected] - clk_out1_design_1_clk_wiz_0_0 [email protected])
Data Path Delay: 4.166ns (logic 1.301ns (31.231%) route 2.865ns (68.769%))
Logic Levels: 15 (CARRY8=2 LUT4=4 LUT5=1 LUT6=8)
Clock Path Skew: 0.106ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.711ns = ( 8.711 - 4.000 )
Source Clock Delay (SCD): 4.283ns
Clock Pessimism Removal (CPR): -0.322ns
Clock Uncertainty: 0.061ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.098ns
Phase Error (PE): 0.000ns
Clock Net Delay (Source): 3.244ns (routing 1.984ns, distribution 1.260ns)
Clock Net Delay (Destination): 3.133ns (routing 1.804ns, distribution 1.329ns)
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_0 rise edge)
0.000 0.000 r
AY26 0.000 0.000 r pgrc0_clk_clk_p (IN)
net (fo=0) 0.000 0.000 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I
HPIOBDIFFINBUF_X1Y154
DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
0.474 0.474 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O
net (fo=1, routed) 0.050 0.524 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT
AY26 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
0.000 0.524 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O
net (fo=1, routed) 0.375 0.899 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0
MMCM_X1Y6 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
-0.127 0.772 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0
net (fo=1, routed) 0.239 1.011 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_0
BUFGCE_X1Y167 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.028 1.039 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
X0Y3 (CLOCK_ROOT) net (fo=74067, routed) 3.244 4.283 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/clk
SLR Crossing[1->0]
SLICE_X11Y204 FDRE r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/offset_reg_reg[2]_replica/C
------------------------------------------------------------------- -------------------
SLICE_X11Y204 FDRE (Prop_FFF2_SLICEM_C_Q)
0.069 4.352 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/offset_reg_reg[2]_replica/Q
net (fo=16, routed) 0.154 4.506 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/I29[1]_repN
SLICE_X11Y205 LUT6 (Prop_G6LUT_SLICEM_I4_O)
0.135 4.641 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/shift_axis_extra_cycle_reg_i_115/O
net (fo=89, routed) 0.544 5.185 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/offset_reg_reg[5]_3
SLICE_X14Y205 LUT5 (Prop_G6LUT_SLICEL_I3_O)
0.114 5.299 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/out_fifo_wstrb_reg_0_31_14_27_i_169/O
net (fo=4, routed) 0.171 5.470 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/out_fifo_wstrb_reg_0_31_14_27_i_169_n_0
SLICE_X14Y204 LUT6 (Prop_H6LUT_SLICEL_I2_O)
0.135 5.605 f design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/out_fifo_wstrb_reg_0_31_28_41_i_111/O
net (fo=4, routed) 0.116 5.721 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/out_fifo_wstrb_reg_0_31_28_41_i_111_n_0
SLICE_X14Y203 LUT6 (Prop_E6LUT_SLICEL_I1_O)
0.134 5.855 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/out_fifo_wstrb_reg_0_31_28_41_i_117/O
net (fo=2, routed) 0.305 6.160 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/out_fifo_wstrb_reg_0_31_28_41_i_117_n_0
SLICE_X15Y201 LUT4 (Prop_C6LUT_SLICEL_I1_O)
0.047 6.207 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/out_fifo_wstrb_reg_0_31_28_41_i_77/O
net (fo=2, routed) 0.091 6.298 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/out_fifo_wstrb_reg_0_31_28_41_i_77_n_0
SLICE_X15Y199 LUT4 (Prop_C6LUT_SLICEL_I3_O)
0.031 6.329 f design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/out_fifo_wstrb_reg_0_31_28_41_i_33/O
net (fo=7, routed) 0.353 6.682 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/out_fifo_wstrb_reg_0_31_28_41_i_33_n_0
SLICE_X16Y190 LUT4 (Prop_B6LUT_SLICEM_I2_O)
0.081 6.763 f design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg[7]_i_153/O
net (fo=1, routed) 0.153 6.916 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg[7]_i_153_n_0
SLICE_X15Y190 LUT6 (Prop_G6LUT_SLICEL_I2_O)
0.082 6.998 f design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg[7]_i_140/O
net (fo=1, routed) 0.177 7.175 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg[7]_i_140_n_0
SLICE_X14Y188 LUT6 (Prop_G6LUT_SLICEL_I1_O)
0.047 7.222 f design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg[7]_i_97/O
net (fo=1, routed) 0.080 7.302 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg[7]_i_97_n_0
SLICE_X14Y187 LUT6 (Prop_D6LUT_SLICEL_I1_O)
0.047 7.349 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg[7]_i_59/O
net (fo=2, routed) 0.087 7.436 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg[7]_i_59_n_0
SLICE_X14Y187 LUT4 (Prop_C6LUT_SLICEL_I3_O)
0.031 7.467 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg[7]_i_34/O
net (fo=2, routed) 0.134 7.601 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg[7]_i_34_n_0
SLICE_X14Y184 LUT6 (Prop_B6LUT_SLICEL_I0_O)
0.048 7.649 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg[7]_i_41/O
net (fo=1, routed) 0.012 7.661 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg[7]_i_41_n_0
SLICE_X14Y184 CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7])
0.166 7.827 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg_reg[7]_i_21/CO[7]
net (fo=1, routed) 0.023 7.850 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg_reg[7]_i_21_n_0
SLICE_X14Y185 CARRY8 (Prop_CARRY8_SLICEL_CI_O[7])
0.103 7.953 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg_reg[15]_i_21/O[7]
net (fo=2, routed) 0.209 8.162 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/length_reg_reg[15]_i_21_n_8
SLICE_X14Y186 LUT6 (Prop_F6LUT_SLICEL_I4_O)
0.031 8.193 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/status_fifo_len_reg_0_31_14_15_i_1_comp/O
net (fo=1, routed) 0.256 8.449 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/status_fifo_len_reg_0_31_14_15/DIA1
SLICE_X16Y186 RAMD32 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/status_fifo_len_reg_0_31_14_15/RAMA_D1/I
------------------------------------------------------------------- -------------------
(clock clk_out1_design_1_clk_wiz_0_0 rise edge)
4.000 4.000 r
AY26 0.000 4.000 r pgrc0_clk_clk_p (IN)
net (fo=0) 0.000 4.000 design_1_i/clk_wiz_0/inst/clkin1_ibufds/I
HPIOBDIFFINBUF_X1Y154
DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
0.418 4.418 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/DIFFINBUF_INST/O
net (fo=1, routed) 0.040 4.458 design_1_i/clk_wiz_0/inst/clkin1_ibufds/OUT
AY26 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
0.000 4.458 r design_1_i/clk_wiz_0/inst/clkin1_ibufds/IBUFCTRL_INST/O
net (fo=1, routed) 0.326 4.784 design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0
MMCM_X1Y6 MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
0.560 5.344 r design_1_i/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0
net (fo=1, routed) 0.210 5.554 design_1_i/clk_wiz_0/inst/clk_out1_design_1_clk_wiz_0_0
BUFGCE_X1Y167 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
0.024 5.578 r design_1_i/clk_wiz_0/inst/clkout1_buf/O
X0Y3 (CLOCK_ROOT) net (fo=74067, routed) 3.133 8.711 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/status_fifo_len_reg_0_31_14_15/WCLK
SLR Crossing[1->0]
SLICE_X16Y186 RAMD32 r design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/status_fifo_len_reg_0_31_14_15/RAMA_D1/CLK
clock pessimism -0.322 8.389
clock uncertainty -0.061 8.328
SLICE_X16Y186 RAMD32 (Setup_A6LUT_SLICEM_CLK_I)
-0.067 8.261 design_1_i/PioNicEngine_0/inst/axiDma/axi_dma_wr_inst/status_fifo_len_reg_0_31_14_15/RAMA_D1
-------------------------------------------------------------------
required time 8.261
arrival time -8.449
-------------------------------------------------------------------
slack -0.187
