Alex Forencich

yeah, I am going to be adding similar constraints to all of the multi-SLR parts. Just have to do some more vivado runs to make sure they all do what...

The NetFPGA SUME needs a lot of work. The Virtex 7 FPGA on there is rather old and slow, and some of the changes that have been made since it...

Sounds like you need to either disable kernel module signature verification and/or secure boot, or sign the kernel module with the appropriate key. Depending on how the kernel was built,...

Presumably you mean `AXIS_PCIE_DATA_WIDTH`? Why would you want to set that to 64? Currently, `CPL_SIZE` is 32, so `SEG_DATA_WIDTH*SEG_COUNT` must be at least `CPL_SIZE*8` (256), so `AXIS_PCIE_DATA_WIDTH` must be at...

64 bit at 250 MHz is probably also going to be lower resource consumption than 128 bit at 125 MHz. What is your use case for that? The issue is...

Have you tried a hot reset of the card before loading the driver? There may be some reset-related issues that need to be rooted out. Usually 100G is pretty reliable,...

@WSEmma There is a micro USB port on the PCIe bracket, near the bottom of the card. It may have a rubber plug in it that you need to pull...

Can you provide any more information about the host system?

First, your PCIe link is only gen 3 x8, so there is no way you're going to break 50-60 Gbps. I would say hitting 40 Gbps reliably is quite reasonable....

I think it depends a bit on exactly what you want to do. One option is to simply increase the configured MTU size, and then the kernel will provide larger...