cocotbext-pcie

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Xilinx US+ Configuration Flow Control Interface incorrect

7

I believe `_run_cfg_fc_logic` for usp_model.py should be combinational instead of clocked to match xilinx behavior also it appears the `_run_cfg_fc_logic` is missing the `sel == 0000` case

bengiac

Non-Transparent Bridge support

1

With the current implementation, does it possible to simulate a non transparent bridge (NTB) ?

ohault

The goal would to a plug into QEMU either a complete simulated PCI express system and/or a simulated PCI express devices

ohault

Issue with offline installation: importing gives syntax error

5

We were able to download package and install offline mode. When doing pip3 list it shows that cocotb-pcie is installed: ``` **/Python-3.9.6/bin/pip3 list Package Version -------------- ---------- cocotb 1.6.0.dev0 cocotb-bus...

haykp

Implement link layer and complete transaction layer

1

Implement link layer, flow control credits, flow control, and TLP replay.

alexforencich

Implement PIPE

2

Implement simulation models for PIPE for operation with PCIe IP cores. Requires #3 and #4.

alexforencich

Implement LTSSM in port models to negotiate link speed and width

alexforencich

Add support for Arria 10 PCIe hard IP core

alexforencich