alaindargelas

Opened this case: https://github.com/YosysHQ/yosys/issues/3428

@mysoreanoop wrote in: https://github.com/chipsalliance/Surelog/issues/3975 I'm trying to backtrack output ports from the topModule this way: 1a. Parse all continuous and procedural assignments. 1b. For each assignment, populate an lhs2rhs map...