openfpga-litex
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Add cart pin synchronization to prevent metastability
Overview
This PR implements proper synchronization for cartridge pins and interface signals to prevent metastability issues when crossing clock domains. It adds a parameterized two-stage synchronizer module and introduces GBA PHI clock generation for cartridge operations.
Key Changes
- Add
cart_pin_synchronizer.sv- reusable two-stage synchronization module with proper bitwise vector operations
- Implement synchronizers for all cartridge banks/pins with synthesis preservation attributes
- Add proper direction signal synchronization with break-before-make protection
- Generate PHI clock (~1.058 MHz) for cartridge timing
- Update signal paths to use synchronized inputs