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Current library can't set output frequency above 150Mhz, 1 line code fix can set DIVBY4 bits correctly to solve this issue

Open sullivanzheng opened this issue 2 years ago • 3 comments

https://github.com/adafruit/Adafruit_Si5351_Library/blob/d849003ae9de089ca6883fb71f479c16d2836e83/Adafruit_SI5351.cpp#L477

This library doesn't set DIVBY4 bits of MultiSynth correctly so that any frequency above 150Mhz (i.e. PLL >600Mhz, divided by 4) is not achievable.

SI5351 and its substitute MS5351 has DIVn_DIVBY4 bits in register 44, 52, 60 (for SI5351A with 3 outputs) at bit[3:2]. Need to set these bits to "11" if MultiSynth need to divide PLL frequency by 4.

Suggested bug fix: Simply modify this line to: sendBuffer[3] = ((P1 & 0x30000) >> 16) | lastRdivValue[output] | (div==4?0B1100:0B0000); to correct this issue. Have tested this on both SI5351A and MS5351M ICs.

I can easily get (without overclocking) 225Mhz output after this bug fixed. And 290Mhz after over clocking PLL to 1.16GHz with MS5351M chip. Of course, this may vary across individual chip.

sullivanzheng avatar May 15 '22 05:05 sullivanzheng