Support for VHDL and SystemVerilog

Open GlenNicholls opened this issue 6 years ago • 5 comments

When will support for VHDL be added (.vhd and .vhdl)? I would guess this is similar to Ada, so probably not much work there. SystemVerilog (.sv)should be the same as verilog.

Oct 23 '19 17:10 GlenNicholls

Hi @GlenNicholls, for VHDL I created a pull request already, see #197 . Verilog is already supported, which should make it pretty easy to extended it for SystemVerilog as well.

Oct 24 '19 15:10 matzesc

Awesome, thanks @matzesc!

Oct 31 '19 20:10 GlenNicholls

I'll get on these soon. Need to get a few fixes ready for a release but I shouldn't be too long. Perhaps this weekend

Oct 31 '19 20:10 aaron-bond

What is the status for VHDL?

Jun 23 '20 22:06 GlenNicholls

@GlenNicholls there was another issue specifically for VHDL (#173 ). As I said in there, it's working for me.

Apr 06 '22 07:04 ghost