Albert Ou

With older versions of the Linux kernel, the provisional page tables created when virtual memory is first enabled can map at most a certain range, hardcoded to be only 128...

It looks like v5.12 and later bring only a partial fix. The VM init code was simplified to statically allocate only a [single 2nd-level page table](https://github.com/torvalds/linux/blob/4357f03d6611753936e4d52fc251b54a6afb1b54/arch/riscv/mm/init.c#L328) (PMD) for the provisional...

> This is to avoid wiping out ephemeral data on your rootfs accidentally. Is this a concern about overwriting a parent's rootfs image that has been modified by the user...

As @qmn responded on the RISC-V sw-dev mailing list, the working copy of mpfr may be corrupted, and refreshing the source directory typically resolves this. If the issue persists, I...

Yes, the emitted Verilog is synthesizable in the same style as rocket-chip. When reading into a synthesis tool, the `SYNTHESIS` macro must be defined in order for non-synthesizable constructs to...

6f35066b6b3c1890e3d98b8b1893bbdcd0f698e5 fixes the bootrom path. The intended bootrom image actually resides in `testchipip`, but the one in `rocket-chip` should also work for running the tests. https://github.com/ucb-bar/hwacha-template/blob/8b30e186bcbf56549204b0e9800bd4f23228d8f7/src/main/scala/example/Configs.scala#L14 I am not able...

This should be fixed as of 94ca56ca74ddf3a64488fd709cb4aeab24b7dac5. The verilator test harness originally from testchipip did not support using the DTM to load the test program and release the cores from...

> Also, there are still some issues in the Makefrag file that cannot parse the output command... `/bin/sh` on some distros (Debian, Ubuntu) defaults to `dash` instead of `bash`. `PIPESTATUS`...

Some submodule URLs in `esp-tools` and `torture` were still using SSH instead of HTTPS, which should be fixed as of commit 1b26b5cad051f8265956ebc816b8e0146014fa4d. The only other "unusual" git feature in `scripts/init-submodules`...

Single-precision scalar-vector multiply: ```asm vfmul.s.vs vv1, vv0, vs0 ``` Most Hwacha vector compute instructions support using shared (scalar) registers for the `rs1`/`rs2`/`rs3` operands. The `.vs` suffix shown above is optional;...