variable 'M_AXIS_TDATA' should not be used in output port connection axivfifo.v":792

[ivansun1688]

Hi,

When I try to make an example to try include axivfifo which conncect dds to mig, I got error as following: variable 'M_AXIS_TDATA' should not be used in output port connection axivfifo.v":792

Would you please give a review.

Thanks

[ZipCPU]

This appears to be a wire vs reg issue. Not all of my tools catch this. Please adjust M_AXIS_TDATA to be declared as an output wire instead of an output reg and try again.

Dan