Dan Gisselquist
Dan Gisselquist
Thank you for this addition. I've wanted to fusesoc enable a lot of my own IP, but ... haven't dug into it enough to make a go at it. This...
It would help if you followed the right interface specification. The DSPI core follows the [Wishbone B4](https://zipcpu.com/zipcpu/2017/11/07/wb-formal.html) pipeline standard, not [Wishbone B3 or Wishbone "classic"](https://wishbone-interconnect.readthedocs.io/en/latest/01_introduction.html). (Wishbone B4 is faster than...
The flash controller issue has been fixed with the introduction of a configuration port. In [my older flash controller](https://github.com/ZipCPU/qspiflash/blob/master/rtl/wbqspiflash.v), you could write to the flash by simply issuing write commands...
Sigh. Without a trace to work from, you're really making this a challenge. What tool can be used to provide a trace? Many. - Most vendor packages (a.k.a. Quartus) will...
Yes, thank you, 109fh.
So ... I decided to do a quick review of your design, and your "clockmem" (a.k.a. clk40 looks like a problem). It appears to be a [separate clock in your...
Fair enough. Let me also remind you that you can only interact with the device in config mode or in memory mapped mode. If you make a mistake and try...
Given that the reset will cause the flash to re-execute its start up script, this simply proves that ... the flash will respond properly when given the proper requests.
One drawback of this approach is that it doesn't directly allow address modification. This is great for switches that don't need to modify their network address, but not so great...