bam
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The current situation is that each SSD can only be controlled by one GPU. Is it possible to achieve control and reading of one SSD by multiple GPUs?
I noticed the code in include/page_cache.h: https://github.com/ZaidQureshi/bam/blob/d20ef4ac5d4513a411422e41caf48562977504dc/include/page_cache.h#L810 Wondering if it should be: ```c++ uint64_t* temp1 = new uint64_t[np]; ``` or ```c++ uint64_t* temp1 = (uint64_t*) malloc(np * sizeof(uint64_t)); ```
Hi, I'm looking at this line of code from (https://github.com/ZaidQureshi/bam/blob/d20ef4ac5d4513a411422e41caf48562977504dc/include/page_cache.h#L775) and I'm trying to understand the meaning of ctrl.ctrl->page_size * uints_per_page in the following snippet: ```c++ const uint32_t uints_per_page =...
Hi there, I'm doing benchmark testing on my machine which is configured with some H800 GPUs and 8 NVMe storages dedicated for the BaM. The GPU is configured with PCIe5...
Creating a thread to keep track of potential enhancements that might need to be added in the future. We do not have access to AMD GPUs to enable this support...
**Describe the bug** A clear and concise description of what the bug is. it is build error **To Reproduce** Steps to reproduce the behavior: following the guide to make libnvm...
**Describe the bug** I encounter a segfault when running the following command `./bin/nvm-block-bench --threads=262144 --blk_size=64 --reqs=1 --pages=262144 --queue_depth=1024 --page_size=512 --num_blks=2097152 --gpu=0 --n_ctrls=1 --num_queues=128 --random=true` gdb shows: ``` Thread 1 "nvm-block-bench"...