mlir-aie
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Xilinx
An MLIR-based toolchain for AMD AI Engine-enabled devices.
Check all the transfer_read memrefs: 1) If the lowest dim has iv, check whether its corresponding loop step is divisible by the vector lanes. 2) For the higher dimension, check...
With the --localize-locks pass converting locks into integer indexes, we no longer need to be restricted to useLock operations existing primarily in CoreOps. Instead, we can simply pass around the...
This patch sets the packet bit when DMABDPacketOp is found in the ShimDMAOp region. This patch also adds a 32x32x32 GEMM unit test. Unfortunately, currently this test case doesn't work...
Antenna Detection feature update. Generates warnings using the MLIR Diagnostic Infrastructure when antennas are in the design. (reupload due to branch error).
When detecting routing errors, there are cases where loops might be present. Develop a method for detecting these loops along the routing path.
Device specific variables: Refactor to separate device, platform, and board information
Clang compilation options were added to aiecc.py (main.py) when targeting petalinux 2021.2 sysroots (like the vck190_bare_prod_2021.2 platform) in order to find the correct library dependencies. See https://github.com/Xilinx/mlir-aie/blob/main/tools/aiecc/aiecc/main.py#L157-L162. This should ideally...
When I run unit_tests/01_memory_read_write unit test, find these errors ```bash >>> python aiecc.py --sysroot=/ --aie-generate-xaiev2 ~/work/new-aie/mlir-aie/test/unit_tests/01_memory_read_write/aie.mlir -I/home/lay/work/new-aie/mlir-aie/runtime_lib /home/lay/work/new-aie/mlir-aie/runtime_lib/test_library.cpp ~/work/new-aie/mlir-aie/test/unit_tests/01_memory_read_write/test.cpp -o test.elf >>> ./test.elf .... MW: 0x20000072000, 0x2, 0x0 MW: 0x20000072008,...
Hi all, I am still very new to this project and still get very lost, but reading through some issues (#106 #77) and @nqdtan's [fork](https://github.com/Xilinx/mlir-aie/commit/14c00ed3234ed7698c6720cb457cc5491d2d9999) of this project, I have...
