libsystemctlm-soc
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Xilinx
SystemC/TLM-2.0 Co-simulation framework
Hi sir, I found there may a bug in the ProcessResp_SN @L2663, because SetWriteToSNDone is called in two place: 1. [req->SetWriteToSNDone(true);](https://github.com/Xilinx/libsystemctlm-soc/blob/42aa8ed780cb9eef3a61bc50ea35ff079a7e6284/tlm-modules/iconnect-chi.h#L2653) @L2653 2. [req->SetWriteToSNDone(true);](https://github.com/Xilinx/libsystemctlm-soc/blob/42aa8ed780cb9eef3a61bc50ea35ff079a7e6284/tlm-modules/iconnect-chi.h#L2694) @L2694 **which will never be called,...
Hi sir: I am trying to integrated the chi here into a system, while I readed the implementation of the chi protocol , I found for a read transaction with...
@ 42aa8ed7 , following the Quickstart instructions in README.md after successfully cloning submodules: ``` cd tests/ make examples-run ``` gives: ``` make[2]: Entering directory '/home/user/libsystemctlm-soc/tests/example-rtl-umi/obj_dir' g++ -I. -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd...
When tlm2apb-bridge transact a writing, slave might fail to sample psel & penable on posedge of pclk.
Xcelium reports C++ type dismatch at code: ``` // file: axi2tlm-bridge.h line:413 for (; i < DATA_BUS_BYTES && m_dataIdx < m_gp->get_data_length(); i++) { if (wstrb.read().bit(i)) { ............ } ``` changed...
Hello, I'm trying to run the refdesign-sim demo, connecting to the Xilinx QEMU VM. The QEMU is running and waiting for connection: ``` (qemu) device_add remote-port-pci-adaptor,bus=rootport1,id=rp0 Failed to connect to...
Hi! I'm trying to use this lib for some co-simulation works but I have some questions about its feasibility for my use case. We have user logic based on XDMA...
In TEST3, the last 4KB should start at 0x102101000.
I am trying to create a way that my software test can notify the simulator for the Programmable Logic (in my case I use QuestaSim) that it has passed or...
