Fixed FPU/SIMD accessibility for EL1 execution

[giorgiocicero]

This patch fixes the configuration of CPACR_EL1 (Architectural Feature Access Control Register) that controls the SIMD/FPU access in case of EL1 execution (enabled with the EL1_NONSECURE and HYP_GUEST macros set to 1 and EL3 macro set to 0 within bspconfig.h). This patch covers both standalone and FreeRTOS BSP.

I am using FreeRTOS executing at EL1 as Guest upon a bare-metal hypervisor. As far as I understood, the SIMD/FPU is allowed only in case of FreeRTOS BSP, while any instruction associated with Advanced SIMD and Floating-point execution shall be trapped in case of standalone BSP.

The FPEN field ([21:20]) of the CPACR_EL1 was erroneously set since the shifting value was 0x20 and there is no guard for distinguishing between standalone and FreeRTOS BSP.

The changes are:

• enable trapping any instruction in EL0/1 that uses registers associated with Advanced SIMD and FP execution for standalone BSP by clearing FPEN field of CPACR_EL1 register
• disable trapping any instruction in EL0/1 that uses registers associated with Advanced SIMD and FP execution for FreeRTOS BSP by setting FPEN field of CPACR_EL1 register

[mubinsyed]

Hi @giorgiocicero,

Thanks for the patch. We have identified this bug recently and fixed it locally. It would be available in 2020.1 release.

Regards, Mubin