Xilinx
XDMA: Implementation of bypass BAR seems to make no sense
Host DMA bypass interface (on bypass BAR) and descriptor bypass modes are, despite similar names, are very different, yet they share implementation. write op copies descriptors from an engine to a mysterious address on bypass BAR, influenced by
#define BYPASS_MODE_SPACING 0x0100 and I found no explanation in docs for this.
But Bypass BAR doesn't have any DMA engines attached to it (as for example shown on Fig. 1 in PG195). As far as I understand it is supposed to function similar to plain "AXI Bridge for PCI Express" IP. It is impossible to use it in such way with current implementation.
This implementation doesn't seem to make any sense. There must be separate implementations for the 2 modes.
Hi Prandr, if your findings are correct, this is an epic fail from Xilinx. Just like the whole XDMA, so at least they kept their style consistent. So DMA Bypass is not working for you? Or Descriptor Bypass? (let's rename it to Descriptor Passthrough?) Also, if you are using DMA Bypass, why do you prefer it over AXI Lite Interface?
I am not using them at the moment, just read the code and wanted to confirm that I am not dumb :D
I have the same confusion as yours，did you try the descriptor bypass read/write?
No, it's unclear, how it is supposed to work. However, in my reworked driver I also added proper implementation for the bypass BAR that uses direct device I/O and removed any claim for support of descriptor bypass.