Run vpl: FINISHED. Run Status: impl ERROR

[rt44477]

Hi, I tried build this part project genDAG

Starting bitstream generation.. [23:01:43] Run vpl: Step impl: Failed [23:01:43] Run vpl: FINISHED. Run Status: impl ERROR

===>The following messages were generated while Compiling (bitstream) accelerator binary: dag_gen_kernel Log file: /home/root7/git/blockchainacceleration/hw/genDAG/build_dir.hw.u55n_gen3x4/link/vivado/vpl/prj/prj.runs/impl_1/runme.log : ERROR: [VPL 101-2] design did not meet timing - Design did not meet timing. One or more unscalable system clocks did not meet their required target frequency. For all system clocks, this design is using 0 nanoseconds as the threshold worst negative slack (WNS) value. List of system clocks with timing failure:

v++_dag_gen_kernel.log

platform xilinx_u55n_gen3x4_xdma_1_202110_1 vivado 2021.1 vitis 2021.1

Yours faithfully

[yluo39github]

same issue

[chunsj]

Vitis 2021.2 fails on the same stage; but with routing related problems.