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Xilinx
Multislot mm support
Memory manager changes for multislot support. This PR has following changes: -> Introduce a memory manager. --> Memory manager initialization is done in two phases. memory manager init is done only once for a device. --> Phase 1 : In the drm init state, read the memory information from platform. This is done even before first xclbin is loaded. Here We read all the available banks and create a drm_mm_init for <start_addr - end_addr>. Also allocated memory for all the stats. This phase is required if build in PS kernel is loading first which doesn't have memory information.
--> Phase 2 : This is done while first XCLBIN is loading, which has memory topology information. In this phase we also
initialized p2p memory. Some platform doesn't have memory information. For that case Phase 1 is also
done here. Here memory initialization is done based on memory topology.
-> xocl_init_mem is done everytime when a new xclbin is loaded. Now this is a link list which has only stats information and memory is allocated based on the start end address of that bank from memory manager.
-> Removed wrapper data structure. I believe we don't need this.
