GlobalSignalRouting.getLCBPinMappings() fails for some pins

[eddieh-xlnx]

GlobalSignalRouting.getLCBMappings() assumes that the sink pin of global nets must be within two hops of a leaf clock buffer (LCB).

This is not always true, for example:

join [find_routing_path -to [get_nodes -of [get_site_pins RAMB36_X7Y53/ADDRENAU]] -from [get_nodes RCLK_INT_L_X68Y269/CLK_LEAF_SITES_0_CLK_LEAF]] \n
RCLK_INT_L_X68Y269/CLK_LEAF_SITES_0_CLK_LEAF
INT_X68Y268/INT_NODE_GLOBAL_11_INT_OUT0
INT_X68Y268/INT_NODE_IMUX_43_INT_OUT0
INT_X68Y268/BOUNCE_W_2_FT1
INT_X68Y267/INT_NODE_IMUX_58_INT_OUT0
INT_X68Y267/IMUX_W46
BRAM_X68Y265/BRAM_BRAM_CORE_3_ADDRENAU_PIN

contrasting to the CLK pin:

join [find_routing_path -to [get_nodes -of [get_site_pins RAMB36_X7Y53/CLKBL]] -from [get_nodes RCLK_INT_L_X68Y269/CLK_LEAF_SITES_0_CLK_LEAF]] \n
RCLK_INT_L_X68Y269/CLK_LEAF_SITES_0_CLK_LEAF
INT_X68Y266/INT_NODE_GLOBAL_0_INT_OUT1
INT_X68Y266/CTRL_W4
BRAM_X68Y265/BRAM_BRAM_CORE_3_CLKBL_PIN

EDIT: For future contributors who will work on this -- a test demonstrating this failure is at https://github.com/Xilinx/RapidWright/pull/758