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Published 20 hours ago • verified publisher icon Xilinx

[Interchange] Create LUT routethru cells if not present

Open eddieh-xlnx opened this issue 2 years ago • 1 comments

Fixes #546

eddieh-xlnx avatar Oct 03 '22 20:10 eddieh-xlnx

Unit Test Results

  42 files    42 suites   9m 13s :stopwatch: 574 tests 566 :heavy_check_mark: 8 :zzz: 0 :x: 587 runs  579 :heavy_check_mark: 8 :zzz: 0 :x:

Results for commit 744ce1f9.

:recycle: This comment has been updated with latest results.

github-actions[bot] avatar Oct 03 '22 20:10 github-actions[bot]