Embedded-Design-Tutorials
Embedded-Design-Tutorials copied to clipboard
Xilinx
using petalinux 2021.2 vitis 2021.2 image from eMMC (sd0) root FS type: initramfs FS boot.bin, image.ub and boot.scr are located at FAT32 partition of the eMMC. image.ub read by u-boot...
https://github.com/Xilinx/Vitis-Tutorials/issues/112 > The `ref_design `_ for this example provides not only the source code for applications, but also a Makefile to run > through the design generation process. To generate...
In [this](https://xilinx.github.io/Embedded-Design-Tutorials/docs/2022.1/build/html/docs/Introduction/Zynq7000-EDT/5-using-gp-port-zynq.html) tutorial (_Using the GP Port in Zynq Devices_), Section '**Testing the PL IP with Prepared Software**' -> 2 (importing sources from [ref_files](https://github.com/Xilinx/Embedded-Design-Tutorials/tree/2022.2/docs/Introduction/Zynq7000-EDT/ref_files)) the tutorial points us to the...
Under "Useful Links" the SmartLynq+ documentation link points to the older SmartLynq document. https://github.com/Xilinx/Embedded-Design-Tutorials/blob/master/docs/Introduction/Versal-EDT/docs/6-system-design-example-HSDP.rst
As title, otherwise build failure. It is likely caused by the following macro `#define FSBL_SD_EXCLUDE_VAL (1U)`
I've been following the Zynq-7000 SoC Embedded Design Tutorial (2023.2) using a Digilent Zybo Z7-20. The cdma-app showed FAIL even though the DMA transfer occurred (I used the Memory inspector...
