Clio
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Clio, ASPLOS'22.
Clio System
Clio is a disaggregated memory system that virtualizes, protects, and manages disaggregated memory at hardware-based memory nodes. More details in our ASPLOS'22 paper here.
This repo contains Clio's FPGA hardware design, host side software, and testing program.
System Architetcure
The Clio hardware includes a new virtual memory system, a customized network system, and a framework for computation offloading
![drawing](https://github.com/WukLab/Clio/raw/master/Documentation/arch.png)
Documentation
Clio system has three major parts: the FPGA bitstream part, the ARM SoC part, and the host-side software.
To compile Clio, see Documentation/compile.md.
To run Clio, see Documentation/run.md.
To debug Clio, see Documentation/debug.md.
ASPLOS'22 Artifact Evaluators, please see Documentation/asplos-ae.md.
Repo Layout
High-level layout:
![drawing](https://github.com/WukLab/Clio/raw/master/Documentation/repo-org.png)
FPGA side stack layout:
![drawing](https://github.com/WukLab/Clio/raw/master/Documentation/repo-org-fpga.png)
Host side stack layout:
![drawing](https://github.com/WukLab/Clio/raw/master/Documentation/repo-org-host.png)
License
MIT
Disclaimer
This is a research prototype. Use at your own risk.
Help
Please use Github Issues.