Mixed blocking and non blocking assignments.

[jera001]

Unfortunately some synthesis tools other than Xilinx vivado does not know how to interpret mixed blocking and non blocking assignments in a clocked process. The design simulates fine but it does not work when compiled on efinix Efinity software. Is there any chance of an updated core?

[Neverforgetme]

mate, I think it is impossible for Mr Wang Xuan may not make any changes and respond to any questions.

How about using the Xilinx vivado software?

[jera001]

I would, and have used Vivado in the past but Xilinx devices are currently unobtanium. I however, just yesterday, got it to work on efinix devices. Turns out the micro sd-card I was using was to new. Works ok with a 5 year old card. So compiler error it wasn't.

[Neverforgetme]

To be honest, I have met this problem when I use 32gb sdhc uhs-1 which is made by sandisk. My problems is that it is always stuck in the ACMD41. When I test timeout/syntaxe/resparg[31], they are all 1. But my program can not run into the CMD2 (card identity)

[jera001]

Got it to work on 32GB SDHC UHS-1 sandisk. Changed the command precount delay value from 24 to 48 in sd_reader.v case(card_state) CMD0 : set_cmd(1, (SIMULATE?128:64000) , 0, 'h00000000); CMD8 : set_cmd(1, 48,/24 ,/ 8, 'h000001aa); CMD55_41: set_cmd(1, 48,/24 ,/ 55, 'h00000000); ACMD41 : set_cmd(1, 48,/24 ,/ 41, 'hc0100000); CMD2 : set_cmd(1, 48,/24 ,/ 2, 'h00000000); CMD3 : set_cmd(1, 48,/24 ,/ 3, 'h00000000); CMD7 : set_cmd(1, 48,/24 ,/ 7, {rca,16'h0}); CMD16 : set_cmd(1, (SIMULATE?128:64000) , 16, 'h00000200);

[WangXuan95]

Hello, for Xilinx (vivado) and Altera (quartus) FPGAs , I'm sure that the 2021 version of this repo is available and stable , since SDv1, SDv2, SDHCv2 were successfully tested at that version on both Xilinx and Altera.

But I made a mistake in 2022.4 : I modified the code but didn't test it on board, causing the bug that @Neverforgetme mentioned. I will fix this bug when I get time in next month, also, I will standardize the code, using non-blocking assignments in all always-structure to let it available on other synthesizer.

Temporarily, I've switch this repo to the older 2021 version. (However, this older version also uses blocking assignments, causing it only works on vivado and quartus)

[WangXuan95]

Hi, I've changed all real registers' assignments to non-blocking assignments (<=). There are some temporary reg variables (not real registers) that still use blocking assignments. You can compile it and try it out, and if you have any questions, please let me know.

Also, I found another key point: my design does not use the sddat1~sddat3 signals, they need to be kept high, otherwise the SD card may enter SPI mode. You can use pull-up resistors on the PCB, or write assign sddat[3:1] = 3'b111 in the FPGA.