WRoenninger

> A crossbar with multiple slave and master ports would contain in its inputs and outputs: > > ```systemverilog > // Slave Ports > input slv_ports_axi_req_t [NumSlvPorts-1:0] slv_ports_req_i, > output...

Yes, as you mentioned, the intend was to have the default ports runtime configurable. However I have not seen this feature being used dynamically yet and see the overhead that...

This behavior was a deliberate design decision I took when writing the module. It was taken to adhere to the AXI4 ordering model (Chapter 6). The previous implementation was interleaving...

Added the `docs/` folder and copied the `axi_xbar.svg/.png` to it. Are the now redundant files for the `axi_xabr` documentation save to delete from the `doc/` folder with this PR?

Seems however that the link to the .png in line `28` to `docs/axi_xbar.png` is still broken. How do I specify this properly, or does it only show up on master?

Is there a possibility to check the pipeline status of a failing gitlab-ci? Just to check if the ci failed on a stall due to a functional failing module, or...

> Why is that? The simulation script currently has 5 different parameters which each get checked for two values in the script. This equates to 32 simulation runs. In the...

Just seen: As is `scripts/axi_intercon_gen.py` will be broken after implementing these changes.

~~Removed now the Cfg struct of `axi_xbar` and the defintion in `axi_pkg`. This resulted in the same removal being done for `axi_lite_xbar`.~~ Edit: This was reverted to keep compatibility for...

Rebased onto current master, also changed around the Bender dependencies to match current tags.