Vinayakamk

i did even this inside isa directory by running make run this produced me elf and .out file which are empty ,does this give me license to declare the instructions...

this is in so much of need!! any help could be welcoming here

Then try creating the all 4 path groups and pass sort by slack CMd. U will the path from start and end point with timing properties of that perticular path

i wish to do a formal verification (logic equalence checks etc) for my designs. i recently came to know about the yosys's sby and eqy tools, but is there any...

thanks ,for the reply sir, but in verilog gl file is also broken while unziping. as u said ,,whether i can remove gzip verliog from make file? ! [image](https://github.com/dineshannayya/riscduino/assets/137029135/c974db1c-b90e-496b-9a0d-aa1b37b5d388)