Trying to parameterize a Verilog module that name is not lower-case causes error.

[piotrva]

When executing a Library.module(), when a Verilog module has non-lower-case name an error occurs. This is due to the fact that both Library.entity() (VHDL) and Library.module() (Verilog) generate call to Library.test_bench(), that makes the name always lower-case.

Above calls trying to parameterize any non-lower-case Verilog module to fail.