VUnit
Parsing of VHDL configurations does not handle spaces
There is a bug in the parsing of VHDL configurations by VUnit. If you have spaces around you architecture instantiations VUnit will not recognize them properly. Taking the example VHDL Configurations as a base we can show this bug by adding some spaces.
This works
-- Configuration declarations
configuration rtl of tb_selecting_dut_with_vhdl_configuration is
for tb
for test_fixture
for dut : dff
use entity work.dff(rtl);
end for;
end for;
end for;
end;
This is valid VHDL but it doesn't work and gives the error: RuntimeError: Ambiguous use of test_lib.dff
configuration rtl of tb_selecting_dut_with_vhdl_configuration is
for tb
for test_fixture
for dut : dff
use entity work.dff( rtl );
end for;
end for;
end for;
end;
The ambiguous use error seems to come from VUnit not recognizing the use entity work.dff( rtl ); statement anymore. I suspect the pattern matching of the VUnit parser does not account for spaces.
The error comes from here: https://github.com/VUnit/vunit/blob/4e30fa124ea84609af0f957dbc55b82adaed1d76/vunit/project.py#L326
I think the parsing of architecture name happens here: https://github.com/VUnit/vunit/blob/4e30fa124ea84609af0f957dbc55b82adaed1d76/vunit/vhdl_parser.py#L1005
Probably, the solution is to add \s* between \(( and between )\) towards the end of that line, i.e., \(\s*( and )\s*\).
