[Bug] `check_equal` and `check_true` raises error for values other than `'0'` and `'1'`

[nselvara]

Hey, there I noticed something strange, while using check_equal or check_true for (un-)signed types. It actually raises an error if we pass any value except '0' and '1' for got resp. expected.

-- This passes
check_equal(got => std_ulogic_vector'("U"), expected => std_ulogic_vector'("U"), msg => "test std_ulogic_vector");
-- These not
check_equal(got => signed'("U"), expected => signed'("U"), msg => "test signed");
check_equal(got => unsigned'("X"), expected => unsigned'("X"), msg => "test unsigned");
check_true(expr => unsigned'("Z") = unsigned'("Z"), msg => "test equality unsigned");

I checked the definition of the (un-)signed types and seems to be that those are just arrays of std_ulogic type:

type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC;
type UNRESOLVED_SIGNED is array (NATURAL range <>) of STD_ULOGIC;

I guess, equality check with values other than number don't pass for (un-)signed types in VHDL resp. excluded in LRM?

if got = expected then