awesome-vhdl icon indicating copy to clipboard operation
awesome-vhdl copied to clipboard

Added libv

Open martinjthompson opened this issue 6 years ago • 4 comments

What is this VHDL project?

A small collection of utilities

What's the difference between this VHDL project and similar ones?

I'm not aware of other time/frequency conversions. The assert with reporting is probably done endless times in other places though!


Anyone who agrees with this pull request could vote for it by adding a :+1: to it, and usually, the maintainer will merge it when votes reach 10.

martinjthompson avatar May 09 '18 17:05 martinjthompson

Other libraries containing time/frequency conversions:

P.S. You can upvote your own PR :)

Paebbels avatar May 09 '18 17:05 Paebbels

Heh - I'm a little out of date then :)

On 9 May 2018 at 19:00, Patrick Lehmann [email protected] wrote:

Other libraries containing time/frequency conversions:

P.S. You can upvote your own PR :)

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/VHDL/awesome-vhdl/pull/6#issuecomment-387823895, or mute the thread https://github.com/notifications/unsubscribe-auth/AAaEIz619nT8QJqbMZT2pUSEXtZDbuJfks5twy6ggaJpZM4T4u6o .

-- [email protected] http://parallelpoints.com/

martinjthompson avatar May 10 '18 18:05 martinjthompson

Your library was a great inspiration, but I personally think that the functionality provided by PoC is even bigger. We use this actively in many entities to specify generic I/O components. So e.g. wie specify the board's system clock frequency, so any counter generating some timing get's adjusted to it's minimal needs.

Paebbels avatar May 10 '18 18:05 Paebbels

Yes, it's likely there's nothing in libv that isn't elsewhere (and priobably better) by now!

On 10 May 2018 at 19:53, Patrick Lehmann [email protected] wrote:

Your library was a great inspiration, but I personally think that the functionality provided by PoC is even bigger. We use this actively in many entities to specify generic I/O components. So e.g. wie specify the board's system clock frequency, so any counter generating some timing get's adjusted to it's minimal needs.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/VHDL/awesome-vhdl/pull/6#issuecomment-388150147, or mute the thread https://github.com/notifications/unsubscribe-auth/AAaEI0orD9R3Nu1Ss3HARjn2K-RG5p1Pks5txIyxgaJpZM4T4u6o .

-- [email protected] http://parallelpoints.com/

martinjthompson avatar May 10 '18 20:05 martinjthompson