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Published 20 hours ago • verified publisher icon VHDL

Dictionary

Open JimLewis opened this issue 3 years ago • 1 comments

https://github.com/VHDL/CoreLib/blob/efe6954672614326fc41b0dbef8cd9395edc8bd9/data_structures/src/Dictionary.vhd#L108

The package is instrumented up to support different sized std_logic_vectors.
In Set, when a key is found, it is "assumed" to be the same size as the current value. Is this an ok assumption? Could the set value be a different size?

JimLewis avatar Feb 03 '21 17:02 JimLewis