Incorrect formatting when a procedure is included in a process

[Rob-McKay]

When you perform formatting of VHDL code which contains a procedure (in a process), the formatting of the procedure is not what I expect and the indenting after end procedure should be indented by one more indent block.

See the example below:

[Schottkyc137]

rust_hdl_vscode does not yet have a formatter. I think that your issue is from a different extension