VHDL-LS
Ignore missing files
As student I use this lsp for some university assignments. The assignments have all the same structure, except some of them are missing a test bench. However I use the same config file symbolical linked in every sub assignment folder, which fails on the assignment without a test bench.
Therfore it would be nice to have an option to ignore missing files (at least for definitions with wildcards).
If I understand you correctly, this is already possible (see the exclude configuration option). If you want to skip a file from being analysed altogether, you can achieve this by excluding it in the vhdl_ls.toml file and setting the nonProjectFiles to ignore (unfortunately this approach isn't documented anywhere)
Doe this help you already?
That's not exactly what I want. I would like to ignore that my wildcard isn't actually selecting any files (so the problem is not a file, but a missing one), since this throws an error in every normal vhdl file on open.