Update Instruction interface to support micro-op fusion

[hal-jones]

Supporting uop fusion appears to be required (or at least, appears to be typically used) for split store address/data instructions, to allow multiple uops to reference and write to a single LSQ entry.

With micro-op fusion, a single micro-op may represent multiple other uops "fused" together. A "fused" uop takes a single slot in the ROB, LSQ (where applicable), and decode/rename pipeline stages, but is split into multiple uops when entering the reservation station; each of these split uops may be dispatched, executed, and written back independently. Once all "child" uops have completed, the parent is marked as ready to commit. The practical benefit of micro-op fusion over regular micro-op generation is that fewer spaces are occupied in various out-of-order buffers, and on Intel processors a macro-op that decodes to a fused uop may use one of the simple decoders instead of requiring the use of the sole complex decoder.

In practice, this will require adjustments to the Instruction interface, allowing the dispatch stage to poll an instruction to determine whether it's a fused uop, and if so, to retrieve and dispatch the component uops instead. These component uops would need to also implement the Instruction interface, but would likely only exist as a thin wrapper around their "parent" instruction, sharing much of the same metadata.