[Bug]: Cannot set Verilog input/output pins to 1 bit

[Gelthir]

Discord Thread

https://discord.com/channels/828292123936948244/1309351705074470974

What happened?

Attempting to change the width of a Verilog output pin to 1 is ignored, 2 seems to be minimum accepted.

Version

0.1225 Beta

What OSes are you seeing the problem on?

Windows

Relevant debug.log output, search next to the exectuable

No response

[Gelthir]

Same issue applies to Veriog input pins.