Multiple writes clarification

[Neo-Zhixing]

https://github.com/Tobski/simple_vulkan_synchronization/blob/a4c7ede63d29e2612d5ae1545d3b507c506fc5ed/thsvs_simpler_vulkan_synchronization.h#L936-L937

Currently we assert that pPrevAccesses and pNextAccesses can have at most one write access for each global barrier. Imagine a scenario like this:

1. RayTracing shader writes to buffer A
2. Compute shader writes to buffer B
3. Pipeline barrier
4. Compute shader reads from buffer A
5. RayTracing shader reads from buffer B

This should be a valid case, but the assertion is asking us to make it "appear on its own." However, we only take one global memory barrier parameter in cmd_pipeline_barrier: https://github.com/Tobski/simple_vulkan_synchronization/blob/a4c7ede63d29e2612d5ae1545d3b507c506fc5ed/thsvs_simpler_vulkan_synchronization.h#L1197

@Tobski Can you clarify what we could do in this case? Thanks.