Tiziano De Matteis

WIP

**Describe the bug** Some particular configurations of GEMM for FPGA currently stall for Xilinx. For Intel, there is a small issue with the generated code. **To Reproduce** Steps to reproduce...

**Describe the bug** When executing a connected component, of an SDFG State, independent "subcomponents" are not executed in parallel. **To Reproduce** Consider the following DaCe program: ```Python import dace import...

Check for applicability of a LibNode expansion

1

It would be nice if, while expanding, we can check that the chosen expansion is applicable and if not, default to something else. In this sense, there should exist also...

**Describe the bug** The Jacobi simple sample fails to produce correct FPGA code (both Xilinx, Intel). This is due to some missing kernel parameter in the generated code, that are...

Integration of a minimal set of SMI functionalities (p2p communications for the moment being). ### Possible solution Introduce the concept of remote streams ### Technical details If SMI should be...

Currently, streams are not properly handled in fpga_transform_state. This will let the codegeneration phase fails in one tries to convert to FPGA DaCe programs that contain stream (e.g. `samples/simple/filter.py`). In...

FPGA polybench sample present unnecessary kernel arguments

2

**Describe the bug** Some of the FPGA polybench kernels (heat-3d, jacobi-1d, jacobi-2d, seidel, nussinov) are codegenerated with unnecessary kernel arguments that prevent their compilation. These arguments are usually loop variables.

**Describe the bug** Some of the FPGA polybench samples fail (3mm, atax, cholesky, correlation, ...) due to check in `sdfg.trace_nested_access` **To Reproduce** Launch sample, convert SDFG to FPGA and then...

Enabling more tests