Tim Hutt

Is that repo intended to replace `riscv-arch-test` then? It seems focused on Wally?

Ah interesting. Is there a plan for how it's going to work? If we can replace `riscv-arch-test` with something better that would be great, but it's going to affect the...

Regenerate the .S files. The seeding issue would be fixed by [this](https://github.com/riscv-non-isa/riscv-arch-test/pull/608) but that can't be tested because of a bug in riscv-isac - clearly it has not even been...

> One of the goals was to avoid needing to install components of the project as Python packages, so instead of the somewhat messy package structure of riscv-isac and riscv-ctg,...

You can *maybe* get away without it, but Typer and Pydantic greatly improve code quality, and I expect they're going to end up using Pyyaml. The current `riscv-arch-tests` has [a...

I can reproduce this. The problem is the code is this: ``` register mseccfg : Seccfg = legalize_mseccfg(Mk_Seccfg(zeros()), zeros()) ``` In `legalize_mseccfg()` it calls `checkPmpNcfgL(63)` which eventually reads `pmpcfg_n`. However...

If you initialise the register then it works: ``` register pmpcfg_n : vector(64, Pmpcfg_ent) = vector_init(Mk_Pmpcfg_ent(zeros())) ```

Yeah maybe time to just require all registers to be initialised full stop. Still you'll probably need to deal with the order anyway I would have thought?

Hmm thinking about this more I'm not sure about it. Maybe what would actually be least confusing is if do something like this: ``` val process_rfvv_single : (rfvvfunct6, bits(1), vregidx,...

I guess it's because by default we use the system libgmp, but the others are unlikely to already be available in package managers. Arguably we could vendor libgmp too and...