LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation

• We would like to maintain a list of resources that utilize Large Language Models to solve promlems in Electronic Design Automation
• Paper Link
• Also see our maintaining list for Awesome Artificial Intelligence for Electronic Design Automation
• Maintained by members in SJTU-Thinklab: Ruizhe Zhong, Xingbo Du

Assistant Chatbot

1. ChipNeMo: Domain-Adapted LLMs for Chip Design
2. New Interaction Paradigm for Complex EDA Software Leveraging GPT
3. From English to PCSEL: LLM helps design and optimize photonic crystal surface emitting lasers
4. RapidGPT: Your Ultimate HDL Pair-Designer

HDL and Script Generation

1. ChatEDA: A Large Language Model Powered Autonomous Agent for EDA
2. ChipNeMo: Domain-Adapted LLMs for Chip Design
3. ChipGPT: How far are we from natural language hardware design
4. CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesis
5. An Empirical Evaluation of Using Large Language Models for Automated Unit Test Generation
6. RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model
7. GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models
8. AutoChip: Automating HDL Generation Using LLM Feedback
9. Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
10. VeriGen: A Large Language Model for Verilog Code Generation
11. Generating Secure Hardware using ChatGPT Resistant to CWEs
12. The Power of Large Language Models for Wireless Communication System Development: A Case Study on FPGA Platform
13. A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
14. RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
15. VerilogEval: Evaluating Large Language Models for Verilog Code Generation
16. Benchmarking Large Language Models for Automated Verilog RTL Code Generation
17. SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
18. Zero-Shot RTL Code Generation with Attention Sink Augmented Large Language Models
19. Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
20. From English to ASIC Hardware Implementation with Large Language Model

Code Analysis and Verification

1. ChipNeMo: Domain-Adapted LLMs for Chip Design
2. LLM4SecHW: Leavering Domain-Specific Large Language Model for Hardware Debugging
3. Unlocking Hardware Security Assurance: The Potential of LLMs
4. RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
5. LLM-assisted Generation of Hardware Assertions
6. Using LLMs to Facilitate Formal Verification of RTL
7. DIVAS: An LLM-based End-to-End Framework for SoC Security Analysis and Policy-based Protection
8. Fixing Hardware Security Bugs with Large Language Models
9. LLM for SoC Security: A Paradigm Shift
10. The Power of Large Language Models for Wireless Communication System Development: A Case Study on FPGA Platform
11. A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
12. SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
13. AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
14. On Hardware Security Bug Code Fixes By Prompting Large Language Models

Large Circuit Models (LCMs)

1. The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models