Add support for latest ZTEX firmware.

[dpifke]

After applying these changes, I can succesfully mine on both my 1.15x and my 1.15y boards. The latter currently only uses a single FPGA; I'm currently working on a (much more invasive) patch to use all four chips, to be applied on top of these (fairly safe) changes.

[TheSeven]

I'm not sure what to do about this. Do you have a clue what exactly those values in the nonce reading result mean, i.e. how this maps to FPGAs, iterations, or whatever? Once this is figured out, it should be fairly straightforward to extend this to multiple FPGAs. The FTDIJTAG module will probably be a good template for this.

[dpifke]

It was written to match the behavior of the current BTCMiner.java code. Without these changes I couldn't mine at all using my MPBM and my 1.15y. Since applying the changes, I've been able to do so successfully, albeit using only the first FPGA.

I believe the intent of the extra nonce stuff is to support bitstreams which have more than one hasher working in parallel. Rather than pipeline everything so you get 1 hash per clock, it's possible to design code that performs X hashes per Y clocks. I'm not aware of any publicly-released bitstreams that do this, but I've played with this technique and it makes the place-and-route a lot easier.

Agree that the multiple FPGA stuff should be straightforward; my intent was to push one piece at a time for ease of testing and merging.