SystemVerilog
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Function regex issue
It seems the regex to recognize sv function has some problem: if the left parenthesis and the function name are not on the same line, the function is not parsed correctly by the regex, as illustrated by the two screenshots below:
When parsed correctly:

When parsed incorrectly:

The problem is that I do not have a good general fix for this: i cannot make the distinction between a function with no return type or a function with a return type and the name on the next line, that's why I'n using the open parenthensis to ensure it correspond to a function name ...
Could you just add an optional newline to the regex so if the parentheses are on a new line it still catches the function name on the previous line?