SystemVerilog
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Reindenting typedefs indents poorly
trafficstars
Code like:
typedef class Class1;
typedef class Class2;
typedef class Class3;
will indent to:
typedef class Class1;
typedef class Class2;
typedef class Class3;
Also, jumping to hierarchy with a typedef just takes you to the typedef instead of the actual class.
The alignment is fixed in the next version of the plugin. For your second remark, I'll need more details to reproduce it
I mean if I have the cursor on a class object and I want to jump to its definition, it will jump to the line where the typedef is declared instead of to the actual class definition. Not sure if that is the plug-in or ST feature though come to think of it.