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https://github.com/The-OpenROAD-Project/OpenSTA/blob/3e2295adfd5ffb7053aa6bb68f31b0eae8f2986f/tcl/Util.tcl#L105 It is more rigorous to examine the composition of tcl identifiers, which begin with a letter and an underscore and consist of a letter, a number, and an underscore.

I am trying to link my design to generate sta reports but then getting an error of core dumped. ![Screenshot from 2023-10-11 09-50-42](https://github.com/The-OpenROAD-Project/OpenSTA/assets/69187224/e0ad6a70-b687-49c9-9869-3d984c0eac79)

In a small ASIC verilog design (with about 42K flops and quite a complete clock definition set) a report_checks report to a destination, (a ROM address bit) lists 168 sources...

I was wondering if there is a description of how it is calculated and used in delay calculation. Output slope is path dependent and if there are multiple paths through...

not sure if there is already a place where I could add lint/test checks to systematically detect typo like this?

s/documentiaton/documentation/g

Hi .I know the path with starting and endpoint.. But I want to know what are all the things ( e.g accumulator,MUX,logic gates) Lying on the path of instrest. How...

The design I am working on is picorv32 So I basically want to reduce the number of gates in the critical path, how do I do that? Also could suggest...

I want to override the library of a liberty_cell. I can use get_property to find out what library it is from, but I could not see an easy way to...

Hi, The memory leak is detected with simple testcase. Here is the log (cmake_san.log at testcase): =1484234==ERROR: LeakSanitizer: detected memory leaks Direct leak of 4 byte(s) in 2 object(s) allocated...