The-OpenROAD-Project
grt/drt: Add support for design using a techno+libs without tie cells
Description
I have a techno which uses libs which don't provide tie cells. I asked the standard cells developers but they don't plan to create tie cells as the analysis showed they are not needed. I created fake lef as a workaround but OR should support this case.
Basically the gate pin should be connected to the power net and the net should be treated as a signal and routed to the nearby rail/followpin in metal 1.
This request should be more or less similar to https://github.com/The-OpenROAD-Project/OpenROAD/issues/8770.
Suggested Solution
No response
Additional Context
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a) if your synthesis tool supports constant propagation, you should only have constants on hard macros. b) there were arguments that tying gate inputs directly to vdd/gnd is not good for esd, use a) c) constants are not good for test coverage, use a) d) you still need tie cells for configuration pins on hard macros, but then you want testable ones.
they don't plan to create tie cells as the analysis showed they are not needed
I'm curious what "the analysis" entailed as I've rarely seen chips without tie cells.
Agreeing with @stefanottili: not having tie cells is bad design. They are extremely easy to create from a cell library perspective.
I don't know either what their analysis is but at least here is the answered I received:
I put a ticket (114614) to ESD team enquiring if there is any ESD risk when connecting MOS gate directly to supply. They confirmed that there is no ESD risk in doing so.
Also Lionel shared a discussion on this topic ; conclusion was that the TIE cells are not mandatory and their purpose is to ease connection to "1" / "0" in digital flow.
So it is OK to proceed with MOS gate connected to Power / Ground for "1" or "0" connection.
Using tie cells is good design but it happens that with legacy old nodes (like an internal 130nm in my case) we have to do without. I can do a request to create them but I don't expect much as the development focus is on newer technos. I think OpenROAD should support this like commercial tools do and discourage it with the warning.
Designing the GDS/LEF for tie cells in a node like 130nm should take an experienced designer under 30 minutes. It's just a single transistor. Having a .lib would be useful, but not strictly required I think.
If you really wanted to avoid making a transistor, you could even design a cell which only connects the power rail to a pin. Take a tap cell from the PDK, remove the active region and well contacts, and then mark the metal as a pin.
I think it is bad practice and not advisable for OR to support not using tie cells.