cts: Failure when several clocks are declared on the same port

[titan73]

Describe the bug

Declarations:

create_clock -name clock1 -period 500      [get_ports clk]
create_clock -name clock2 -period 250 -add [get_ports clk]

Expected Behavior

Should not fail.

Environment

OR 27d6fae69da083c1e2bdd6ff83cc8d4dfefdaeed

To Reproduce

Test case: multi_clocks.zip

Relevant log output

[WARNING CTS-0104] Clock wire resistance/capacitance values are zero.
Use set_wire_rc to set them.
[INFO CTS-0050] Root buffer is gf180mcu_fd_sc_mcu9t5v0__buf_8.
[INFO CTS-0051] Sink buffer is gf180mcu_fd_sc_mcu9t5v0__buf_8.
[INFO CTS-0052] The following clock buffers will be used for CTS:
                    gf180mcu_fd_sc_mcu9t5v0__buf_8
[INFO CTS-0049] Characterization buffer is gf180mcu_fd_sc_mcu9t5v0__buf_8.
[ERROR CTS-0114] Clock clock2 overlaps a previous clock.
Error: pnr.tcl, 23 CTS-0114
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Screenshots

No response

Additional Context

No response