CTS tech characterization enhancement

[arthurjolo]

Description

For the design ihp-sg13g2/riscvi CTS is not inserting buffers in some levels, the image shows the net clknet_0_clk where the level 0 clock buffer (clkbuf_0_clk) is driving all the buffers on the level 4.

The tech characterization step determines that for levels 1-3 no buffer is the best option. This makes me believe that there might be an error or some improvements to be done on tech characterization.

Suggested Solution

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Additional Context

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[arthurjolo]

[maliberty]

How many sinks are there?

[arthurjolo]

There are 1056 sinks in this design, and CTS creates 5 levels.

[maliberty]

That seems like a lot. How large are the sink clusters?

[arthurjolo]

The sinks are clustered in groups of 8 to respect the max_fanout limit.