Improve the buffering of simple wires

[maliberty]

Describe the bug

The new buffer_varying_lengths test for rsz shows cases where the buffering needs improvement. Two-pin wires are increasing length are generated and buffered:

The buffering is far from optimal with some wires showing one buffer right next to the driver.

Expected Behavior

Optimal buffering for all lengths.

Environment

Head of master

To Reproduce

Run the test

Relevant log output

No response

Screenshots

No response

Additional Context

No response

[maliberty]

For example moving instance wire15 to the middle (x=450um) reduces the slack from -0.14 to -0.12