Enable wrong way routing on ASAP7 M1-M3

[antonblanchard]

Description

The ASAP7 techlef disables wrong way routing on all metal layers. M1-M3 is modelled on single exposure EUV, so wrong way routing should be possible. Enabling it would improve routing out of standard cells.

The design rules for these layers are a bit confusing to me:

There is only one rule for side to side spacing (M1.S.1), but it is qualified by > 36 nm. The other spacing rules all read as EOL rules to me, so they don't apply to spacing between wires.

I've found some extra information in Vinay's dissertation:

Patterned M1-M3 lines have a 36 nm 2-D pitch and minimum line width of 18 nm is
enforced by the DRs. 

T2T spacing for narrow lines is 31 nm following Van Setten et al. [39], while
wider lines can have a smaller tip-to-tip spacing at 27 nm [59]. As per the PDK
DRs, lines narrower than 24 nm are considered thin lines and those wider than
this value are considered as wide lines. This threshold value was determined
based on the minimum LISD width, since LISD routes near the power rails become
the limiting cases for T2T spacing. 

A moderate T2S spacing of 25 nm follows the results demonstrated by Van Setten
et al. [17].

Corner-to-corner EUV metal spacing of 20 nm enables via placement to metals on
parallel tracks at the minimum possible via spacing of 26 nm with 5 nm EUV
upper metal end-cap to allow full enclosure.

This suggests to me that our wire spacing is 18nm for all lengths.

I'm also not sure how to encode all the T2T and T2S rules in the LEF format. We might have to take the worst case (31mm) and apply it to all EOL spacing.

Suggested Solution

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Additional Context

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