Enable wrong way routing on ASAP7 M1-M3

[antonblanchard]

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Description

The ASAP7 techlef disables wrong way routing on all metal layers. M1-M3 is modelled on single exposure EUV, so wrong way routing should be possible. Enabling it would improve routing out of standard cells.

The design rules for these layers are a bit confusing to me:

There is only one rule for side to side spacing (M1.S.1), but it is qualified by > 36 nm. The other spacing rules all read as EOL rules to me, so they don't apply to spacing between wires.

I've found some extra information in Vinay's dissertation:

Patterned M1-M3 lines have a 36 nm 2-D pitch and minimum line width of 18 nm is
enforced by the DRs. 

T2T spacing for narrow lines is 31 nm following Van Setten et al. [39], while
wider lines can have a smaller tip-to-tip spacing at 27 nm [59]. As per the PDK
DRs, lines narrower than 24 nm are considered thin lines and those wider than
this value are considered as wide lines. This threshold value was determined
based on the minimum LISD width, since LISD routes near the power rails become
the limiting cases for T2T spacing. 

A moderate T2S spacing of 25 nm follows the results demonstrated by Van Setten
et al. [17].

Corner-to-corner EUV metal spacing of 20 nm enables via placement to metals on
parallel tracks at the minimum possible via spacing of 26 nm with 5 nm EUV
upper metal end-cap to allow full enclosure.

This suggests to me that our wire spacing is 18nm for all lengths.

I'm also not sure how to encode all the T2T and T2S rules in the LEF format. We might have to take the worst case (31mm) and apply it to all EOL spacing.

Suggested Solution

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Additional Context

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[antonblanchard]

For reference, here is the rules for M1 in the current techlef. I'm not sure why we are setting our minimum length to be 36nm:

LAYER M2
  TYPE ROUTING ;
  DIRECTION HORIZONTAL ;
 WIDTH 0.018 ; # Min Width
 SPACING 0.018 ; # Min Spacing

 OFFSET -0.27 ;

  #  MINSIZE is set so that the minimum lenght of a segment is 36nm. At the proper rule size of
  #  31nm, the lines can't be minimum space. This causes DRCs (like crazy). Same for M3
  #  MINSIZE 0.112 0.072 ; 
  # area is adjusted to match this (Nanoroute requires both AREA and MINSIZE)

 AREA 0.000666 ;
 MINSIZE 0.037 0.018 ;

 PITCH 0.045 0.036 ;

  # this enforces the correct routing tracks on M2 with wide M2 power rails

 PROPERTY LEF58_PITCH "
 PITCH 0.036 FIRSTLASTPITCH 0.045
   ;
 " ;

  # this checks for distance in any direction so is not correct
  # 0.070 is to avoid conflicts with the adjacent lines. This should be caught by CORNERSPACING below
  #   SPACING 0.124 ENDOFLINE 0.1 WITHIN 0.070 ;

 PROPERTY LEF58_SPACING
 " SPACING 0.018 ENDOFLINE 0.025 WITHIN 0.02 ENDTOEND 0.031
 PARALLELEDGE 0.025 WITHIN 0.02 ; " ;

 PROPERTY LEF58_EOLKEEPOUT "
 EOLKEEPOUT 0.025 EXTENSION 0.0 0.0125 0.031 CORNERONLY ;
 " ;

 PROPERTY LEF58_CORNERSPACING "
 CORNERSPACING CONVEXCORNER WIDTH 0.0 SPACING 0.02 ;
 " ; # CORNER to CORNER SPACING Rule

  # Originally no width table for M2 since it is the follow rails. 
  # They can be 1x or 2x (2x causes DRCs on SAV V1). However, this seems to allow a double width M2
  # on vias, which violates. Thus, this is added. Note that wide power follow rails will violate.

 PROPERTY LEF58_WIDTHTABLE "
 WIDTHTABLE 0.018 0.09 0.162 0.234 0.306 0.378 ;
 " ;

 PROPERTY LEF58_RIGHTWAYONGRIDONLY "
      RIGHTWAYONGRIDONLY ;
 " ;

 PROPERTY LEF58_RECTONLY "
      RECTONLY ;
 " ;

END M2